Electrostatic discharge (ESD) has been around since the beginning of time. It is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. However, this natural phenomenon has only become an issue with the widespread use of semiconductor based integrated circuits and electronics.
All materials (insulators and conductors alike) are sources of ESD. These materials are lumped together in what is known as the triboelectric series, which defines the materials associated with positive or negative charges. Positive charges accumulate predominantly on human skin or animal fur. Negative charges are more common to synthetic materials such as plastics. The amount of electrostatic charge that can accumulate on any item, whether that charge be positive or negative, is dependent on the material and its capacity to store a charge.
The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate between which a current can flow. A gate dielectric is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
An integrated circuit may be subjected to an ESD event during the manufacturing process, assembly handling and in the ultimate system application. The energy associated with this transient discharge can easily damage the fragile devices present within the IC.
In the processing and handling of integrated circuits, ESD may originate from any number of sources such as a mechanical chip carrier, a plastic chip storage device, or even human interaction with the process. In each case it is possible that the integrated circuit is subjected to a voltage that is many times greater than its design voltage. The human body, for example, can store a charge equal to 250 picofarads. This correlates into a stored charge that can be as high as 25,000V. For integrated circuits that operate at voltages of less than, for example, 5V (volts), an electrostatic discharge on the order of several thousand volts can be devastating.
External pins or pads form the connection points for the integrated circuit to the outside world and therefore also serve as pathways for ESD events. An ESD event applied to a pad may couple the ESD voltage exceeding several thousand volts to circuitry coupled to the pad. Therefore, the coupling of ESD to the external pins is also of particular concern to the IC package and circuit designer.
In one conventional IC ESD protection scheme, often referred to as a dynamic trigger scheme, special clamp circuits are often used to shunt ESD current between the IC power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active metal oxide semiconductor field effect transistor (MOSFET) clamp circuit, typically consists of three functional elements: an RC detector or trigger circuit, several stages of inverters and a large MOSFET transistor. The detector circuit is designed to respond to an applied ESD event but remain inactive during normal operation of the IC. The inverter stages are used to amplify the detector circuit output in order to drive the gate terminal of the large MOSFET transistor. The large MOSFET transistor, connected between the two power supply rails, acts as the primary ESD current dissipation device in the clamp circuit. Active MOSFET clamp circuits typically rely on only MOSFET action to shunt ESD current between the rails. Since the peak current in an ESD event may be on the order of amperes, very large MOSFET transistor sizes are required. Generally speaking, these arrangements are limited to ICs of two-rail constructions, e.g., Vdd and Vss rails, wherein all the gates are or should be driven to full Vdd potential.
Integrated circuit constructions of a tri-rail design provide a high or very high drain potential rail, e.g., VHdd 30V-100V or higher potential. Gate potentials are held substantially lower, e.g., VLdd˜<6V. In these arrangements, the conventional RC circuit triggered clamp does not work.
Accordingly, it is desirable to provide ESD protection that is active and effective for ICs of a tri-rail design. In particular, the ESD protection should be effective in IC arrangements providing for VLdd substantially less than VHdd, i.e., VLdd<<VHdd.
Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.